Whether designing test measurement equipment or automotive lidar analog front ends (AFEs), hardware designers using modern high-speed data converters face serious challenges with high frequency inputs, outputs, clock speeds, and digital interfaces. These problems may include problems with your field programmable gate array. Before building the system, make sure your first design channel will work or determine the best modeling of the system.

 

 

Engineers often evaluate the most important chips on the test bench before starting a new hardware design. Once the equipment required for a typical evaluation board is obtained, component evaluation is usually performed at the desired power and signal sources. TI In most cases, it will provide an on-board power supply and clock so you can run the board with minimal test bench equipment and more practical power and signal sources.

 

After performance verification, a more complete evaluation board diagram and layout can be used as part of the reference design subsystem. Our data acquisition and pattern generation tools support CMOS, LVDS, and JESD204, along with the software needed to operate them. Using the Evaluation Board User Guide, your high-speed data converter can get most evaluation boards up and running in less than 10 minutes.

 

As systems become more complex, you may need to evaluate a wider range of use cases. You may need an evaluation board. If your assessment needs become complex, you can use it Python, MATLAB, LabVIEW, or C++ software to communicate directly with devices through device evaluation boards, acquisition card solutions, and test bench devices. Some good examples of our panel support include some good examples of panel support for LVDS/CMOS TSW1400EVM and TSW14J56EVM for JESD204B Serialer-destrayer (SerDes) protocol devices.

 

TI also supports a single PC complete system level model, multi-evaluation module prototype. For example, with XilinxFPGA development kits such as KCU105 or VCU118 connected to multiple analog-to-digital converters (ADCs) or digital-to-analog converters (Dacs), both send and receive channels can be tested simultaneously.

 

How do you solve one of the biggest problems you might want to solve? The FPGA gets the data. Although LVDS and CMOS are a simple interface, they have extremely limited speed to support each foot on the device. With widespread support for newer high-speed data converters, 1GSPS these interfaces have either lost market share or complicated design.

 

Setting the microelectronics industry open standard JEDEC created JESD by 1204 + support, 204.5Gbps this issue is resolved by the channel rate difference. All the same. JESD204 minimizes the number of feet, but it adds complexity to the interface by either encoding and serializing or deserializing and decoding.

 

Until now, you have to rely mainly on its JESD204 intellectual property (IP) block and the support provided by the FPGA vendor. All the same. IP blocks can work fine, but they provide any device that supports any configuration. This means it can be difficult to understand and assign your specific use cases. You need to put a lot of effort into designing your own IP or finding a vendor IP from a third party IP. However, if there is a problem, the third party IP needs help and support for implementation.

 

TI's own JESD204 Rapid Design IP can be pre-configured and optimized for your FPGA platform, data converter, and JESD204 mode. IP requires fewer FPGA resources per specific use and can also be customized. Another advantage is implementing it. JESD204 links only take hours or days, not weeks or months.

 

 

Direct radio frequency (RF) sampling and the combination of ultra-fast SerDes with high-speed data converters are becoming more common, and RF's ability to model signal integrity has become the ability to model signal integrity. Traditionally, most suppliers only provide input impedance information from the supplier ADC in the S-parameter model, but the target of high-frequency input devices that provide input impedance information TI, such as ADC12DJ3200, ADC12DJ5200RF and ADC12QJ1600-Q1, is up to 8GHz sampling frequency. The existing S-parameter model, Contains impedance and frequency response information.
With this new model, the expected behavior of the device can be simulated and impedance matching can be optimized. TI's strategy is to provide these models to support devices with high input and output frequencies, where impedance matching and the required frequency response are more challenging.

 

On the digital interface side of the data converter, the Input/Output Buffer Information Specification (IBIS), which is a common model available for CMOS and LVDS pins to provide physical information and physical information DC and AC type behavior. For most behaviors that use high speed. JESD204SerDes These models have been improved for the new data converter IBIS- Algorithm Modeling Interface (AMI) and include useful information to help apply balance, pre-weighted or post-weighted. IBIS-AMI provides you with the modeling capabilities you need to properly use the board for the first time, while achieving good bit error rates, signal integrity of the data link, and stability.

 

 

Whether you have designed with high-speed data converters for a while or are not familiar with high-speed design, don't worry because TI is designing an easy-to-use high-speed data converter. Create a complete development environment and simplify all work.

 

With off-the-shelf IP that facilitates FPGA integration, accurate RF-stabilized system models and a flexible set of system models, scalable and automated evaluation modules, you can shorten firmware development time by months, reduce expensive design cycles, and speed high-speed design from concept to prototype.