Texas Instruments' XIO2000A/XIO2000AI PCI EXPRESS to PCI Bus conversion bridge fully complies with the PCI EXPRESS to PCI/ PCI-X bridge specification. The XIO2000A/XIO2000AI Bridge supports eight published and four unpublished transactions simultaneously, with each enabled virtual channel (VC) used for downstream traffic. For upstream traffic, each VC can support up to 6 published and 4 unpublished transactions at the same time.

     TI XIO2000A/XIO2000AI Bridges support two independent vc. The second VC is optimized for synchronous traffic types and QoS applications. In addition, the bridge supports advanced error reporting capabilities, including the Extended CRC (ECRC). In order to take full advantage of these two features, you need to supplement firmware or software. A robust pipeline architecture was implemented to minimize system delays across the bridge. If a parity error is detected, packet poisoning is supported by both upstream and downstream operations