Intel has announced the industry's first implementation of backside power delivery technology on product-level test chips to meet the performance needs of the next era of computing. As Intel's industry-leading backside power solution, PowerVia will be available on Intel 20A process nodes in the first half of 2024. By moving the power cord to the back of the wafer, PowerVia addresses the growing interconnection bottleneck in chip unit area microscaling.

 

Ben Sell, vice president of technology development at Intel, said: "PowerVia is an important milestone in Intel's ongoing 'five process nodes in four years' plan and our commitment to integrate a trillion transistors in a single package by 2030. "By using the pilot-produced process nodes and their test chips, Intel has reduced the risk of using backside power for advanced process nodes, allowing us to bring backside power technology to market one process node ahead of our competitors."

Development of a test chip code-named "Blue Sky Creek". Product testing helped Intel refine its PowerVia backside power technology. PowerVia, expected to launch in 2024 with the Intel 20A process node, is the industry's first to power the back of a chip, solving a decades-long interconnection bottleneck.

 

Intel kept the development of PowerVia technology and transistors separate to ensure that PowerVia could be properly used in the production of Intel 20A and Intel 18A process chips. Before integrating with the RibbonFET transistor, which will also be rolled out with the Intel 20A process node, PowerVia ran tests on its internal test nodes to continually debug and ensure it was functioning well. Using and testing PowerVia on test chips, Intel confirmed that the technology can significantly improve the efficiency of chip use, with cell utilization exceeding 90 percent, and help achieve large transistor miniaturization, allowing chip designers to improve product performance and energy efficiency.

 

Intel will present the findings in two papers at the VLSI Symposium in Kyoto, Japan, June 11-16.

 

As a backside power solution that leads the competition by a wide margin, PowerVia enables chip designers, including Intel Foundry Services (IFS) customers, to achieve faster energy efficiency and performance improvements. Intel has long been committed to introducing industry-critical innovations such as strained silicon, Hi-K metal gates, and FinFET transistors to continue advancing Moore's Law. With the introduction of PowerVia and RibbonFET all-surround gate technologies in 2024, Intel will continue to lead the industry in chip design and process technology innovation.

 

By being the first to introduce PowerVia technology, Intel can help chip designers break through the growing interconnection bottleneck. A growing number of use cases, including AI or graphical computing, require smaller, denser, and more powerful transistors to meet the growing demand for computing power. From decades ago to the present, the power and signal lines in the transistor architecture have been "occupying" the same space in the wafer. By structurally separating the wiring of these two, chip performance and energy efficiency can be improved, providing customers with better products. Backside power supply is critical for transistor miniaturization, allowing chip designers to increase transistor density without sacrificing resources, leading to significant increases in power and performance.

 

                                                                                           

 

 

In addition, the Intel 20A and Intel 18A process nodes will feature both PowerVia backside power and RibbonFET fully surround gate technology. As a new way to power transistors, backside power technology also brings new challenges in terms of heat dissipation and commissioning design.

 

By keeping the development of PowerVia and RibbonFET separate, Intel was able to quickly address these challenges and ensure that PowerVia technology can be implemented in chips based on Intel 20A and Intel 18A process nodes. Intel developed cooling technology to avoid overheating problems, and the commissioning team developed new technology to ensure that the various issues that arose during commissioning of this new transistor design structure were properly addressed. As a result, prior to its integration into the RibbonFET transistor architecture, PowerVia achieved quite high yield and reliability indicators in testing, demonstrating the expected value of this technology.

 

PowerVia's tests also take advantage of design rules introduced by extreme ultraviolet lithography (EUV). In the test results, the standard cell utilization rate in most areas of the chip is more than 90%, and the cell density is also significantly increased, which is expected to reduce the cost. Tests also showed that PowerVia reduced platform voltage by 30% and achieved a frequency benefit of 6%. The PowerVia test chip also demonstrated good heat dissipation characteristics, in line with the higher power density that logic miniaturization is expected to achieve.